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| NB6L14 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer Multi-Level Inputs with Internal Termination Description http://onsemi.com MARKING DIAGRAM* 1 QFN-16 MN SUFFIX CASE 485G 16 NB6L 14 ALYWG G The NB6L14 is a 3.0 GHz differential 1:4 LVPECL fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB6L14 to accept various logic standards, such as LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREF_AC reference output can be used to rebias capacitor-coupled differential or single-ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB6L14 is a member of the ECLinPS MAXTM family of high performance clock and data products. Features * * * * * * * * * * * Maximum Input Clock Frequency > 2.5 GHz, Typical < 20 ps Within Device Output Skew 330 ps Typical Propagation Delay 145 ps Typical Rise and Fall Times Differential LVPECL Outputs, 720 mV Amplitude, Typical LVPECL Mode Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V Internal 50 W Input Termination Resistors Provided VREF_AC Reference Output Voltage -40C to +85C Ambient Operating Temperature Available in 3 mm x 3 mm 16 Pin QFN These are Pb-Free Devices A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. D Q Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 December, 2006 - Rev. 0 1 Publication Order Number: NB6L14/D NB6L14 Q0 Q0 16 Q1 Q1 Q2 Q2 1 2 3 4 5 Q3 6 Q3 7 VCC 8 EN Q0 15 VCC GND 14 13 12 IN 11 VT 10 VREF_AC 9 IN IN 50 W VT 50 W /IN Exposed Pad (EP) /Q0 Q1 /Q1 Q2 EN VREF_AC D Q CLK /Q2 Q3 /Q3 Figure 2. QFN-16 Pinout (Top View) Table 1. EN TRUTH TABLE IN 0 1 x IN 1 0 x EN 1 1 0 Q0:Q3 0 1 0+ Figure 3. Logic Diagram Q0:Q3 1 0 1+ + = On next negative transition of the input signal (IN). x = Don't care. Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Name Q1 Q1 Q2 Q2 Q3 Q3 VCC EN I/O LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output - LVTTL/LVCMOS Description Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC-2.0 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Positive Supply Voltage Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT. Output Voltage Reference for capacitor-coupled inputs, only. Internal 100 W center-tapped Termination Pin for IN and IN. LVPECL, CML, LVDS, HSTL - - LVPECL Output LVPECL Output - Non-inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT. Negative Supply Voltage Positive Supply Voltage Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC-2.0 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC-2.0 V. The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 9 10 11 12 13 14 15 16 - IN VREF_AC VT IN GND VCC Q0 Q0 EP LVPECL, CML, LVDS, HSTL 1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self-oscillation. http://onsemi.com 2 NB6L14 Table 3. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Human Body Model Machine Model QFN-16 Oxygen Index: 28 to 34 Value > 4 kV > 100 V Level 1 UL 94 V-0 @ 0.125 in Table 4. MAXIMUM RATINGS Symbol VCC VIo IIN IVREF_AC IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input/Output Input Current Source or Sink Current (IN/IN) Source or Sink Current on VT Pin Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm (Note 3) QFN-16 QFN-16 QFN-16 Continuous Surge "2.0 50 100 -40 to +85 -65 to +150 42 35 4 265 mA mA mA C C C/W C/W C/W C Condition 1 GND = 0 V GND = 0 V -0.5 V v VIo v VCC + 0.5 V Condition 2 Rating 4.0 4.0 "50 Unit V V mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L14 Table 5. DC CHARACTERISTICS, Multi-Level Inputs, LVPECL Outputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40C to +85C Symbol ICC VOH Characteristic Power Supply Current (Inputs and Outputs Open) Min 35 Typ 47 Max 65 Unit mA LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS Output HIGH Voltage (Notes 4 and 5) (Q, Q) VCC = 3.3 V VCC = 2.5 V VOL Output LOW Voltage (Notes 4 and 5) (Q, Q) VCC = 3.3 V VCC = 2.5 V DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (See Figures 5 and 6) Vth VIH VIL VISE VREFAC VREFAC VIHD VILD VCMR VID IIH IIL Output Reference Voltage VCC - 1.525 1200 GND 1150 100 IN/IN IN/IN -10 -50 VCC - 1.425 VCC - 1.325 VCC VIHD - 100 VCC - 50 2800 50 10 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 7 and 8) (Note 7) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) (Note 8) Differential Input Voltage (IN-IN) (VIHD-VILD) Input HIGH Current (VT Open) Input LOW Current (VT Open) mV mV mV mV mA mA Input Threshold Reference Voltage Range (Note 6) Single-Ended Input High Voltage Single-Ended Input LOW Voltage Single-Ended Input Voltage Amplitude (VIH - VIL) 1125 Vth + 75 VEE 150 VCC - 75 VCC Vth - 75 2800 mV mV mV mV VCC - 1145 2155 1355 VCC - 1945 1355 555 VCC - 1020 2280 1480 VCC - 1875 1475 675 VCC - 895 2405 1605 VCC - 1695 1605 805 mV mV LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS VIH VIL IIH IIL RTIN RDIFF_IN Input HIGH Voltage Input LOW Voltage Input HIGH Current, VCC = VIN = 3.63 V Input LOW Current, VCC = 3.63 V, VIN = 0 V Internal Input Termination Resistor (IN to VT) Differential Input Resistance (IN to IN) 2.0 GND -10 -150 VCC 0.8 50 0 V V mA mA TERMINATION RESISTORS 40 80 50 100 60 120 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with 50 W to VCC - 2.0 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single-ended mode. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 8. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L14 Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40C to +85C (Note 9) Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) (Note 10) 1.25 GHz 1.25 GHz fin 2.0 GHz 2.0 GHz fin 3.0 GHz Propagation Delay Set-Up Time (Note 11) Hold Time (Note 11) Within-Device Skew (Note 12) Device to Device Skew (Note 13) tJITTER RMS Random Jitter (Note 14) Peak-to-Peak Data Dependent Jitter (Note 15) VINPP tr,tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) Output Rise/Fall Times @ Full Output Swing (20%-80%) fIN = 2.5 GHz fIN = 2.5 Gb/s 100 70 150 14 2800 200 mV ps IN to Q EN to IN, IN EN to IN, IN 300 300 5.0 20 150 1.0 ps Min 550 380 250 Typ 700 500 320 350 Max Unit mV tPD tS tH tSKEW ps ps ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC - 2.0 V. Input edge rates 40 ps (20%-80%). 10. Input and output voltage swing is a single-ended measurement operating in differential mode. 11. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply. 12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions. 13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2^23-1 and K28.5 at 2.5Gb/s. http://onsemi.com 5 NB6L14 INn VTn INn 50 W 50 W Figure 4. Input Structure VIH Vth VIL IN VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin Vth IN Vth Vthmin GND Figure 5. Differential Input Driven Single-Ended VCC Figure 6. Vth Diagram VIH(MAX) VIL D VCMR D VIH VID = VIHD - VILD VIL Figure 7. Differential Inputs Driven Differentially VIH GND VIL(MIN) Figure 8. VCMR Diagram IN IN Q Q tPD VOUTPP = VOH(Q) - VOL(Q) tPD VINPP = VIH(IN) - VIL(IN) Figure 9. AC Reference Measurement http://onsemi.com 6 NB6L14 VCC VCC VCC VCC Zo = 50 W LVPECL Driver VT = VCC - 2 V Zo = 50 W NB6L14 IN 50 W 50 W IN LVDS Driver Zo = 50 W VT = Open Zo = 50 W NB6L14 IN 50 W 50 W IN GND GND GND GND Figure 10. LVPECL Interface Figure 11. LVDS Interface VCC VCC Zo = 50 W CML Driver VT = VCC Zo = 50 W NB6L14 IN 50 W 50 W IN GND GND Figure 12. Standard 50 W Load CML Interface VCC VCC VCC VCC Zo = 50 W Differential Driver VT = VREF_AC* Zo = 50 W NB6L14 IN 50 W 50 W IN Single-Ended Driver Zo = 50 W VT = VREF_AC* NB6L14 IN 50 W 50 W IN (Open) GND Figure 13. Capacitor-Coupled Differential Interface (VT Connected to VREFAC) GND GND Figure 14. Capacitor-Coupled Single-Ended Interface (VT Connected to VREFAC) GND *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 7 NB6L14 VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 800 700 600 500 400 300 200 100 0 0 1 2 3 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) EN VCC/2 tS VINPP tpd tH VCC/2 /IN IN /Q Q VOUTPP Figure 16. EN Timing Diagram Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V Figure 17. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 8 NB6L14 ORDERING INFORMATION Device NB6L14MNG NB6L14MNR2G Package QFN-16, 3x3 mm (Pb-Free) QFN-16, 3x3 mm (Pb-Free) Shipping 123 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB6L14 PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. CC CC CC TOP VIEW (A3) SIDE VIEW D2 5 E A A1 SEATING PLANE C e SOLDERING FOOTPRINT* 8 EXPOSED PAD 9 E2 12 0.575 0.022 3.25 0.128 0.30 0.012 EXPOSED PAD e 3.25 0.128 1.50 0.059 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 NB6L14/D |
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